(Corporate) Product Selection & Strategy Formulation Essay

(Corporate) Product Selection & Strategy Formulation - Essay Example Apple Inc is even enjoying the overwhelming performance in the technology industry is associated with the continuous success and dominance (Abraham 2012). In corporate strategy there are two types of diversification which are: linked and constrained. Companies that use linked diversification enter new business when they are linked with other business they are already operating, if they use constrained diversification, they enter only in new business if it is based on core resources. Apple uses the constrained diversification, Apple is a personal computer company and its business utilizes its core resources in developing the hardware and software such as, iPod, iPad, iPhone, and Apple TV that allows the Apple to share its resources among the business. This even creates the economics of scope, and that create cost savings for Apple Inc., as their resources are shared across all the multiple businesses. Apple follows two strategies which are: Growth Strategy and Stability strategy (Abraham 2012). As the company has not reached to the optimum performance; therefore, there is a requirement for reaching at the optimum performance, this helps the company in expanding its profits, and market share, sales, and market coverage and product mix among the other accounting variables and market. Some of the other strategies utilized for enhancing eth growth include the market penetration enhancement in order to ensure the provision of efficient services. Another growth strategy of the Company is vertical integration, which is an efficient strategy for enhancing the growth, in that Apple Inc., takes activities which are performed by its suppliers or business in its distribution or channel. Diversification strategy is also used by the company in taking effective move for enhancing the growth; in this case the company must use the potential business ventures for enhancing its operations. The

Static And Dynamic Cmos Cascode Voltage Switch Logic Circuits Computer Science Essay

Static And Dynamic Cmos Cascode Voltage Switch Logic Circuits Computer Science Essay This paper presents a dual rail logic network based static and dynamic CMOS cascode voltage switch logic (CVSL) circuits for improving the functional efficiency and low power consumption. The logic design strategic is achieved in CVSL by cascading differential pairs of FET devices are capable of processing Boolean functions up to (2N-1) input variables within a single circuit delay. Potentially CVSL is twice as dense as primitive NAND/NOR logic, and is compatible with existing design automation tools and relieving the device/process complexity burden for CVSL designs. Significant performance and density improvements with simultaneous reduction in power consumption have been investigated using cadence-90 nm technology. The power requirements for the static and dynamic cascode voltage switch logic circuits are compared Index Terms- cascode voltage switch logic (CVSL), Dual rail logic, CMOS VLSI circuit, cadence tools INTRODUCTION In recent years, most of the digital systems are static complementary metal-oxide-semiconductor (CMOS) due to their robust design nature which can implement reliable circuits with excellent noise margin. However, the demand for high-performance digital systems requires continuously faster CMOS circuit speed. Dynamic circuits are proven to have better circuit performance. But unfortunately, these dynamic design styles suffer from charge sharing, low noise margin, complexity of design, and difficulty in testing. Recently, several researchers have attempted to use pass-gate logic style to realize static and high performance designs in different digital systems [1-2]. Pass-gate logics gain their speed over the traditional static CMOS design due to their high logic functionality and reduction in the number of pFET transistors. However, the degradation of pull-up performance for the pass-gate design in the long circuit chain is the major obstacle for most designers to use. Recently, CMOS c ircuit design technique based cascode voltage switch logic (CVSL) is proposed with numerous advantages over the conventional static CMOS [3]. The domino CMOS, NORA and pseudo-NMOS technique is only effective in non-complementary logic circuits and it cannot apply directly to complementary logic functions. But, CVSL circuits can be applied to complementary logic families. Potential advantages include reduced circuit delay, higher layout density, lower power consumption and extended logic flexibility [4]. CVSL have been used to implement high-performance arithmetic circuits such as fast multiplications, ROM, RAM as well as pipelined DSP circuits. CVSL is very suitable for asynchronous designs when logic works at that time only the clocks are running; remaining time is off. This reduces power consumption, especially for large and complex circuits [5]. Dual rail logic network families are becoming increasingly important for advanced technologies because of the very small amount of charge required to hold a logic state. The cascode-voltage-switch logic gates are evaluated for improved the functional efficiency using 90 nm and 65 nm technology CMOS processes [6]. This paper describes dual rail logic network based static and dynamic CMOS cascode voltage switch logic (CVSL) circuits for improving the functional efficiency and power reduction. Significant performance and density improvements with simultaneous reduction in power consumption have been investigated using cadence. The power requirements for the static and dynamic are CVSL compared. design of CMOS CVSL circuit Cascode voltage switch logic is a dual-rail logic family. The dual-rail logic based differential CVSL gates are provides the potential of having high fan-in which leads to a reduction in logic depth, high speed, and the capability of generating completion signals for asynchronous operations. A) Dual rail Logic concept: The dual rail logic structure is consists of two-pFET are cross-coupled to form a simple latch that provides complementary outputs and; the latch is driven by an nFET network that can be viewed as two complementary switching functions. The dual rail logic circuits are more complex than single rail logic circuit, but the dual rail circuit can be faster than single rail circuit [6]. VDD 0 to1 swing 0 (a) Switching waveform for single rail logic VDD 0 to1 swing 0 (a) Switching waveform for dual rail logic Fig 1 Switching action for single and dual rail network The slew rate is simply the rate of change of the output voltage in time. A large slew rate implies a fast switching speed. In case of single rail circuit is generated output, but dual rail logic circuit, both and are generate as output of the gates that is shown in Fig 1. The logic variable is taken to be the difference signalthat effective of slew rate is defines as This illustrate that dual rail circuit intrinsically exhibits faster switching speed than single rail network. In practical the dual rail logic has some problems; increased circuit complexity, increased interconnects required in the layout and timing issues become critical. These problems have been investigated in this static and dynamic differential cascode voltage switch logic circuits. B) Static CVSL: Static differential cascode switch logic circuits usually consist of a push-pull load by pFET and a pair of interrelated (requiring both true and complement signals) binary decision trees by nFET. The Differential CVSL tree is properly designed into two ways, such that: (1) When the input vector is the true of the switching function, that node is disconnected from ground and node is connected to ground by a unique conducting path through the tree. (2) When the input vector is false of, the reverse holds. The logic trees may be further minimized from the full differential form using logic minimization algorithms. This version, which might be termed a static CVSL gate, is lower than a conventional complementary gate employing a p-tree and n-tree. This because switching action, the p pull-ups have to fight the n pull-down trees. VDD pFET Latch pFET2 pFET1 nFET Logic Array Fig 3 Static CMOS CVSL gate circuit A design procedure for differential CVSL circuits using the pictorial nature of the Karnaugh map is proposed. A CMOS cell designed with this procedure is compared with the corresponding gate logic design. A CVSL circuit of the Boolean function is given by that is shown in Fig 2. Note that only 12 transistors are required for this differential CVSL circuit design, two p-transistors and ten n-transistors instead of 10 p-transistors and 10 n-transistors using a NAND-NAND configuration or conventional gate logic design. The transistor pFET latching circuit is consists of two stable states. The conductions of the source-gate voltage on the devices are given as The behavior of the latches is that and is andare voltage complements in this circuit, so one is high while other is low. The latching is induced by nFET switching network, which biases pFET1 into conduction from that time With pFET1 conducting, rises to, which drives pFET2 into cutoff from that time This represents one stable state of the latch. The voltage is pulled to, which gives and biases pFET2 into conduction and pFET1 into cutoff. From this principle, there is no direct path for current flow from to ground for either situation, so that only leakage currents exist. C) Dynamic CVSL: The static CVSL logic gate can be transformed into dynamic circuit by rewiring the pFET latch to the clock-driven arrangement, shown in Fig 3. This eliminates the feedback loop and changes the two-pFET into precharge devices that are controlled by the clock. When the value of clock is zero, drives both pFET into conduction mode that result is precharging of the output nodes. To avoid DC-current flow during this event, an evaluation nFET is controlled by the clock, so it is OFF during the precharge time. VDD nFET Combinational network Differential Inputs Clock Clock (precharge) pFET1 pFET2 Fig 3 Basic structure of a dynamic CVSL gate circuit The precharge clock is zero at event, which allows the voltages across both and to precharge to value of When the clock change to the value is one, the circuit is driven into the evaluation phase. nFET is ON and the input signals are valid. For the case true signals switch is open and is held high while complementary switch is closed and discharges to; The output voltages are initially complementary. However, the left output voltage is subject to the usual dynamic problems of charge sharing and charge leakage, which reduces its value in time. As with all dynamic logic circuits, this gives rise to a minimum clock frequency. The pFET charge is controlled by the output states and. This dynamic cascade switch logic circuit allows with small aspect ratio for charge compensation without excessive current flowing onto the node. Simulation result and analysis The performance of the static and dynamic cascode voltage switch logic circuits designed and evaluated through cadence-gpdk90 nm technology. The static CMOS cell designed CVSL circuit of the Boolean function is given by. The differential input signals A, B, C, D, and E and also complementary input signals are applied to the pull-down (nFET network) network of the circuit. The transient response voltage is set as 1 V with 0.1 ns rise/fall time. The cross-coupled latch is provides complementary outputs and that is shown in Fig 4 A B C D E Q Fig 4 Simulation waveforms for static CVSL circuit Clock A B C D Q Fig 5 Simulation waveforms for dynamic CVSL circuit The dynamic CMOS cell designed CVSL circuit of the Boolean function is given byas a four XOR gate implementation. This is just two-domino gates operating on true and complement inputs with a minimized logic tree. The transient response voltage is set as 1 V with 0.1 ns rise/fall time. The cross-coupled latch is provides complementary outputs and that is shown in Fig 5 The static and dynamic CVSL circuits power consumption is calculated and given in table 1 Table 1 Static and dynamic CVSL Power consumption CMOS Logic Power consumption Static CVSL 166 uW Dynamic CVSL 224 uW Conclusions This paper implements a dual rail logic circuit design technique for CMOS differential cascade voltage switch circuits. This CVSL gates facilitates that improving the functional efficiency and low power consumption. The static and dynamic CMOS differential CVSL circuits have been investigated using cadence-gpdk90 nm technology.

Scuba Trip :: essays research papers

On May 22, 1994 it was my ninth birthday. My mom and dad decided to go on a cruise to the Bahamas. We went on one of the Carnival cruise ships. This boat was the biggest boats I ever saw. When we rushed to get on the cruise ship I saw that there were so many rooms and shops. My favorite room was the Game room, when I entered the game room there were so many games and seemed like there were hundreds and hundreds of them. I started to get bored so I left. When I went to back to our room my dad was thinking about going scuba diving. The following morning my dad planned to go scuba diving when all the tourist went to go sight seeing on the island. We went to the scuba shop and rented all the gear. When the boat came I put on all the gear. For example, the air tanks, goggles, and the regulator. When we got on the boat we had to sit on the edge, so we could flip over the side. Finally, the boat stopped and I could barely see the islands. The captain said not to go past the big cones. I was pretty scared because the water was so deep, but I finally jumped off. Scuba diving was scary so all I did was follow my dad. I finally stop being afraid and looked at all the colors that were weird and unusual. The colors were hot orange and dark red. My favorite coral was the one with the hair on it. It was pretty cool because fish would enter, but would not leave because the coral would eat them! The fish I saw was cool and the only fish I knew was the Angel fish. I knew this fish because of all the colors it had. The other fish were big and had the biggest teeth I ever saw, but I didn't know what they were called.

On His Arrival at the Age of Twenty- Three Poem Analysis Essay

On his arrival at the age of twenty-three, written by John Milton was created during the puritan period. John Milton was born in cheapside, London, in 1608, he grew up in a wealthy family that gave Milton all the opportunity’s to be well educated and attend Cambridge University one of the most highly decorated schools in Europe and the World. Milton grew up during the puritan age, literature during the puritan age shows the effects of social and religious conflicts, these thoughts effect how Milton wrote poetry and in this poem he reflects on his religious beliefs. At the age of 43 Milton was completely blind which affected his writing after that period, although he wrote this poem before that time allowing a different view of the world and religion. One thing to understand about Milton’s sonnets is their topical range was that he was not a writer of love sonnets. Milton writes political sonnets, occasional sonnets, elegiac sonnets, and sonnets of personal meditation, like this one. The result of the puritan period was a loss of freedom, severe persecution for all and a decline in literary progress (Hodson, February, 2013). On his arrival at the age of twenty-three was most likely written in 1632 at a crucial time in Milton’s life, just after his graduation from Cambridge. Milton here acknowledges that he may not seem as mature as some of his contemporaries but expresses a desire to use his talents well and his trust in God’s will for him over time. On his arrival at the age of twenty-three comments on how a man’s life has gone by, what he’s done and achieved and what role God plays into the life of humanity. The poem shows the concerns that Milton had about his career when he was young and still hadn’t chosen his own way in life. In this famous work of his we don’t see a celebration of a birthday but a problem that the young gentleman faces as time passes by. The author uses many metaphors and symbols in order to give a more vivid image of his problem, and at the end he gives a solution to this problem. In fact, this problem is relevant even today, when young people have to decide on a career. Also as time goes by people ask them more often what they have done in their life. Milton places a tone of despair and hope all into one poem, he’s aware he hasn’t done anything worthwhile in his life yet but believes God has still given him time to, the theme of the novel is that time goes quickly and if you leave your time in to the hands of God he will be on the right path in life, but also the crisis of faith and putting your life into Gods hands. Grant-3 Grant-3 Milton worries that time has passed too quickly. He has been at Cambridge studying, but has had little time to fulfill what he sees as his destiny. Milton is aware he is a talented poet, but instead of writing poetry, he has been studying. This precipitates a crisis of faith for the poet, who worries he has wasted precious time. But maybe the poet’s talent, which â€Å"be it less or more,† (Milton line 9) will be less when he is mature. He worries, although he is still confident of his future. About fifty years after Milton’s death, however, this poem was named â€Å"On His Having Arrived at the Age of Twenty-Three. † This title was immediately popular and has endured the time since his death, even if some scholars of Milton wonder whether in saying that â€Å"Time† has â€Å"Stolen† his â€Å"three-and-twentieth year† Milton is actually saying that he is commemorating in this poem his twenty-fourth and not his twenty-third. (Poetry for Students,  ©2013 Gale Cengage). Milton wrote in a Sonnet that had an a,b,b,a c,d,d,c rhyme style. The Petrarchan Sonnet was used during this time period, a Petrarchan sonnet into two distinct parts: the octave (the first eight lines) and the sestet (the last six lines). The octave usually poses a problem, depicts a situation, or offers an observation. The sestet usually provides a resolution of the problem or brings the matter to a conclusion. This sets up the poem for a problem proposed and a solution to solve everything (Hodson, February, 2013) Milton uses the structure to his advantage and his poses the problem of asting his time or â€Å" But my late spring no bud or blossom shew’th† (Milton line 4) and having no achievements yet. To the solution that â€Å" Toward which Time leads me, and the will of Heaven† God will lead him to what right and how he should live his life and use his talents to please God and get into heaven. In on his arrival at the age of twenty-three Milton is both the writer behind the poem and the speaker of it. This shows the poem i s about him and his experience with time. Grant-4 Grant-4 The though development throughout the poem is very intriguing and uses careful diction and metaphors to get his point across. In the first and second lines â€Å"How soon hath Time, the subtle thief of youth, Stolen on his wing my three-and-twentieth year! † (Milton 1,2). Milton personifies Time meaning Father Time that steal your youth then he uses a metaphor of a bird to represent time after and how Father time stole his Twenty-three years of youth. Just like someone stealing an object, the job is done quick and goes unnoticed till a later time just like time creeps up on all of us. Milton goes on to say he hasn’t been able to have any achievements yet. Next Milton says â€Å" Perhaps my semblance might deceive the truth, that I to mandhood am arrived so near; and inward ripeness doth much less appear† (Milton 4,5,6). The poet remarks that he does not seem as old as he is and the truth that he is practically a man. Inward ripeness continues the natural metaphor of bud and Grant-5 Grant-5 lossom in line 4; the poet has more maturity or ripeness inside than he shows outside, although others are â€Å" more timely-happy spirits endu’th† (Milton 8) meaning that they are happy being there age. This is where the shift from Octave to sestet occurs. He has stated the problem that live has gone by so fast he hasn’t been able to get an achievements and how he’s matured more then anyone else. Allow ing for a depressing tone by using words like stolen, no bud, deceive and a late spring to perceive that his time and talents have been completely waster so far. Where the octave found dissonance between his inner and outward states of maturity, the sestet’s answer is that time and the will of heaven will even things out according to plan. The sestet and solution begins with him realizing that weather he achieves something in his life now or later it will still be measured in the strictest even (Milton 11). Noting the multiple puns used by Milton in this line: â€Å"measure† could mean a musical measure or a line of verse; â€Å"even† may be an adjective modifying â€Å"measure† or may lead the reader into the next line, â€Å"even to that same lot. Milton often places adjectives both before and after nouns, and he likewise often lets the word at the end of a line work in two different ways in each line (encyclopedia. com). Regardless of how much maturity there is he is being judged equally to everyone else. The final three lines tell the audience that Milton will let God lead him to where ever he wants him to be and leaves his decision to God or the â€Å"taskmaster†. â€Å"Time leads me, and the will of Heaven† (Milton 12) Father time lets life go on and Milton will follow the will of the heavens. Milton then goes on and ends the poem by saying â€Å"I have grace to use†¦ in my great Taskmaster’s eye† (Milton, 11,12). Just like God chose Milton’s talents so will his destiny be chosen. Grant-6 Grant-6 The theme Milton developed throughout the poem was one of time going by quickly and the crisis of faith, the hard decision of putting all of it in God, although this would be easy for Milton to do back in the times of the puritans because that is what they believed in, although this day and age is would be a lot different. That’s the tremendous part of this poem, its applicable to every day society and life, we can use it to learn and be better. The crisis created by Milton’s awareness of the passage of time is one that can be resolved by the poet’s choice to put his future in God’s hands. In the first eight lines of the poem, Milton worries that time has passed too quickly. He has been at Cambridge studying, but has had little time to fulfill what he sees as his destiny. Milton is aware he is a talented poet, but instead of writing poetry, he has been studying. This precipitates a crisis of faith for the poet, who worries he has wasted precious time. Although he soon realizes God will lead him in the correct path with time and he can use his talent of poetry to the best of his ability. Milton used a cunning way and the sonnet format to produce a poem that can be read and studied throughout the ages and still be applicable to that day. Religion and the crisis of faith will always be a hot topic and its up to personal opinion to figure out which one you should choose. Milton and his puritan views allowed him to pick God easily although someone like Robert Herrick a cavalier in his days, would choose a carefree life so they live while they can now, â€Å"times, still succeed the former† (Herrick, To the Virgins, to make much of time, line 12). Throughout the poem Milton uses nature imagery for metaphors and produces and affective tone of despair and hope between the octave and sestet, also putting a theme of the how time passes very quickly and the crisis of faith.

ICT- Is the understanding of different information and verifying information from data and knowledge

ICT- Is the understanding of different information and verifying information from data and knowledge. How information is communicated and the different types of technology involved. Systems involving computers. Transfer of data and the different types of transfers.ICT does not always involve computers any sort of data being processed into information involves ICT. The Impact of ICT on the music industry This assignment will describe how ICT has affected the general public via the music industry. Music is everywhere nowadays in many different forms but many people do not realise how much of it is ICT based. It's amazing how much of music now relies on computers to run. Music is usually stored in digital format on CD, Minidisk or DVD's. All stages of music production require some sought of ICT involvement from recording to actual CD manufacture . The musician will record the music via microphones that will record and then computers will be used to enhance the quality of the music and then the final touches are added. The internet has also benefited the music industry as people can download music very quickly efficiently but this has also meant that the rate of piracy has increased. Most people wouldn't believe how much it is costing the artists and producers, the figure I millions. Broadband has also helped step up the downloading music from the internet especially from peer to peer networks such as KAZAA. An example of a major internet piracy bust would be Audio galaxy which was closed down due to it releasing music without licenses. ICT has meant that music can be stored instantly and randomly so that it can be edited and mixed for production even by home users. Music has become portable and even phones nowadays have MIDI ring tones that can be transferred using a PC. Phones even allow music recorded onto them for later listening. This just shows how many day to day products are being integrated with music technology and how important music is becoming to society. Most phones that are being released currently come with integrated radio and also stereo headphones. Storing music on computers has meant the urge for more memory and the reason memory on computers is required so much is due to the storage of music. Although ICT has created many new jobs it has also meant that many jobs have been lost due to the fact many jobs have become automated e.g. CD production. An amazing event involving a surprising computer program called EMI (Experiments in Musical Instruments) performed at a concert by writing Mozart's 42nd symphony but the amazing thing is that Mozart only wrote 41. This program was able to replace a musician and compile a whole symphony. This program is able to recognise a composer's signature (the distinctive pattern a composer tends to use over and over again). This shows how computers are more and more replacing humans and doing their jobs. Computers have also meant that many new highly skilled jobs are on offer for people who have degrees in the computer section. Overall ICT has affected society as a whole and day by day more and more people are becoming dependant on computers. Nearly everything runs on or is guided by computers and most scary of all our lives balance on the computers. Young people have also become addicted to games and surfing the net causing parents a major problem.